Race Hazards and Clock Skew

In a synchronous system (where a single clock is shared by all sequential elements) almost all timing problems can be overcome by reducing the speed of the clock. The exception is a race hazard where data arrives too early at the D input of a flip-flop allowing the data to pass through one cycle too early.

To avoid hazard:

t_d1 + t_pQ + t_comb > t_d2 + t_hold

Where:

• t_d1 is the clock delay seen at the first D-type due to the clock distribution
• t_pQ is the Clock to Q propagation delay for the first D-type
• t_comb is the delay through the combinational logic
• t_d2 is the clock delay seen at the second D-type due to the clock distribution
• t_hold is the minimum hold time for the second D-type

this can be re-written as:

t_skew < t_comb + t_pQ - t_hold

Where:

• t_skew is the clock skew (= t_d2 - t_d1)

In this study we will consider the worst case where there is no combinational logic delay (this is the case most likely to result in a hazard).

The equation for hazard avoidance now gives us an upper limit for the permitted clock skew in terms of characteristics of a D-Type:

t_skew < t_pQ - t_hold

Cross Simulation and Intra-Assignment Delays

With a cross simulation we simulate a behavioural module (e.g. controller) alongside a structural module (e.g. datapath).

Since the behavioual module will not include a model for the delay in the clock buffer there is a potential problem as the equation becomes:

t_{clock_delay(structural)} < t_{pQ(behavioural)} - t_{hold(structural)}

The solution is to ensure that t_{pQ(behavioural)} is sufficiently large. This Clock to Q delay must be added in for all registers updated within a procedural block controlled by always_ff @(posedge Clock).

The delays can be seen in the code snippet below:

  always_ff @(posedge Clock, negedge nReset)
    if ( ! nReset )
      begin
        started <= 0;
        toggled <= 0;
        count <= 0;
      end
    else
      begin
        if (( started == 1 ) && ( toggled == 0 ))
          count <= #20 count + 1;
        else
          count <= #20 count - 3;
        started <= #20 1;
        toggled <= #20 ! toggled;
      end

Notes

• a delay of #20 will be sufficient provided that the timeunit setting in the behavioural file matches the one in the structural file (in this case #20 is interpretted as 20 transistor delays).
• the #20 delays are not included within the reset clause since they are included to model Clock to Q propagation delays (not nReset to Q propagation delays).
• the delay is included as an intra-assignment delay:

     regSignal <= #20 newValue
  

  rather than an inter-statement delay:

     #20 regSignal <= newValue
  

  the first form correctly models the Clock to Q propagation delay where the newValue is evaluated on the rising edge of the Clock and regSignal is updated #20 later - the second inter-statement form would not be suitable as it would delay the evaluation of newValue (potentially causing another race hazard) there would also be a knock-on delay for all subsequent statements.
• this arrangement of delays works with non-blocking assignments "<=" but not with blocking assignments "=" where the addition of an intra-assignment delay will result is a knock-on delay for all subsequent statements.

D-Type Timing

For successful operation, data must be available for at least t_setup before the rising clock edge and at least t_hold after the rising clock edge.

The output will be stable and valid t_pQ after the rising clock edge.