This course aims to provide an understanding of basic VLSI layout and circuit design principles. In particular, to look at how CAD tools are utilized in designing digital integrated circuits. For more details see the course syllabus. In addition to the syllabus, a course overview is provided for part III students making Options Choices.

Lecture Notes for 2023-2024:

• Introduction - ...unedited

1. SystemVerilog Hardware Description Language - ...unedited
2. State Machine Design using SystemVerilog - ...unedited
3. Gate Matrix Design - ...unedited
4. Bitslice Design
5. Pad Ring and Floor Planning

• For MSc Students only
  MSc students will additionally attend the Integrated Circuit Design theory lectures

• General- Report Writing Guidelines
• Interpretation of feedback - Equivalent marks for letter grades

Assignments for 2023-2024:

• Mini Design Exercise 1
  • Sweeping parameter values in HSpice
  • Electronic Handin Deadline 16:00 Wednesday 25^th October

• Mask Level Layout using L-Edit -- MSc Students only
  -- experimental system - please report problems to Iain McNally
  • Electronic Handin Deadline 16:00 Tuesday 7^th November

• Mini Design Exercise 2
  • Electronic Handin Deadline 16:00 Wednesday 15^th November

• Design Exercise 3
  • Files Submission
    • Deadline 16:00 Monday 4^th December
      Early submission of files will result in enhanced feedback.
    • Files: Electronic Handin (C-Bass)
  • Characterisation and Cell Library Databook Documentation
    • How to Find Input Capacitance Using Spice by Kostas Pagiamtzis
    • Example Standard Cell Databook
      - yours won't look like this one but it it is useful to see what a real cell library databook looks like.
  • Design Exercise Report
    • Report Writing Guidelines
    • Division of Labour Form
    • Deadline 16:00 Wednesday 6^th December
    • Report: Electronic Handin (C-Bass)
    • Report: Plagiarism Check (TurnItIn)
  • Documentation: Cell Library Databook + Design Exercise Report
    • Documentation Specification

• Design Exercise 4
  • Race Hazards, Clock Skew, Cross Simulation & Intra-Assignment Delays -- how and why to use "#20" delays in your SystemVerilog controller
  • For full chip routing: multiplier.net, multiplier.sv
  • Preparation for Handin -- Draft
  • Files Submission
    • Deadline 16:00 Friday 12^th January
      Early submission of files will result in enhanced feedback.
    • Files: Electronic Handin (C-Bass)
  • Supporting Figures
    • Mark Zwolinski's notes on ASM charts
    • Documentation Deadline 16:00 Friday 19^th January
    • Figures: Electronic Handin (C-Bass)

Laboratory Course:

This course is supported by the CAD Tools and Techniques laboratory course. The course makes use of required CAD and other software

Associated Lecture Course:

This course is closely associated with the Integrated Circuit Design course which is either taken prior to or concurrently with this course.