A long-term strategic goal of the ESD Group is to sustain and advance our current research in SoC design with the overall aim of reducing the design time and cost - attacking the design gap. In the immediate future we will focus on addressing and developing novel solutions to some key design and reliability problems that are emerging from deep-submicron (DSM) technology. A platform grant will enable the Group to develop these new strategic directions by enabling it to pump prime adventurous research projects in design methods and tools for DSM system-on-chip. These are essentially solutions to the "Big Chip" problem, and include: low power design automation of hardware/software co-design, system reliability through built-in testability and repair; and automatic generation of transistor-level analogue IP cores from system-level descriptions.

The Group has significant strength in these areas and the grant will facilitate the expansion of these and provide an effective means of keeping abreast of new developments and ahead of international competition. The grant will also allow the Group to build a number of demonstrators to validate the methods and tools developed, accelerating the acceptance of these new techniques by academia and industry, and with the intention of further commercially exploiting the tools. Also, the grant will provide resources to enable staff to spend time visiting research groups, and host reciprocal visits.




This project, which is collaboration between the School of Electronics and Computer Science at the University of Southampton and the Department of Electrical, Electronic and Computer Engineering at the University of Newcastle, focuses on the development of scalable, reliable and energy-efficient interconnection technology needed by future multi-billion-transistor system-on-chips (SoCs) designed using nanometer CMOS technology. This is a timely and necessary investigation if the microelectronics industry is to continue to produce SoCs for future application at affordable cost, as identified by the 2003 International Technology Roadmap for Semiconductors. Emphasis will be placed upon the employment of the emerging concept of Network-on-Chip (NoC) proposed to overcome complex on-chip communication problems, where SoC cores communicate with each other using packets through interconnection network, thus providing support for communication infrastructure re-use, reliable and power efficient interconnection technology. For this research we will exploit expertise available at the collaborating universities that has recently produced efficient and low-power HW/SW co-design techniques that allow SoC designers to explore different system architectural designs (single/multi processors, hardware (ASIC and/or FPGA), asynchronous communication mechanisms (ACMs) and synchronization. The research will be carried out in close collaboration with Prof P. Eles (Linkoping University, Sweden), Prof. L. Lavagno, Politecnico di Torino, Prof. L. Benini (Bologna University), and MBDA UK.




This project addresses the problem of increasing cost of test of systems-on-chip (SoC). The main objective of this research is to develop design for testability (DFT) techniques to reduce the cost of testing complex digital systems consisting of embedded cores. Emphasis will be placed upon the employment of test resource partitioning, where most of the test is generated on chip, thus providing support for low cost testers. The developed test techniques will be validated using real-life examples. The work will be carried out in collaboration with ARM, Cambridge.




Until recently design-for-test (DFT) and low power IC design represented two separate research directions. The increasing complexity of modern chips transformed testability and power dissipation into conflicting design objectives. This proposal seeks to bring these two directions together by investigating and developing efficient built-in-self-test (BIST) techniques and architectures that are compatible with low power IC design methods. This proposal aims to investigate in detail some of the promising low power DFT techniques (in particular PC-TSS) that have been recently developed at the University of Southampton. The availability of low power BIST techniques and architectures allow IC designers to address concurrently design and test with the aim of generating self-testable designs that are not only optimised in terms of silicon area but also dissipate less power during test than in functional mode, hence resulting in safer testing. An industrial case study will be used to validate the developed techniques and BIST architectures, including the design and fabrication of a demonstrator chip. The work will be carried out in close collaboration with Philips Semiconductors (UK), and University of Iowa (USA).




A Wireless Sensor Network (WSN) consists of a collection of small, locally powered, intelligent sensor nodes that communicate detected events over a wireless channel (typically through multi-hop routing). WSNs are continuing to receive an escalating research interest, due in part to the considerable range of applications that they are suited to. These applications include environmental monitoring, smart buildings, smart structures, object tracking, healthcare, security and defence.

One of the key challenges facing researchers is in overcoming the limited network lifetime inherent in the small locally powered sensor nodes. This project aims to investigate a network management algorithm (not a routing algorithm) to maximise network lifetime through exploiting energy harvesting and energy management, considering the importance of data, and by using only local (or selfish) decisions to minimise negotiation overheads. Additionally, the system will be simulated, analysed and implemented.




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In recent years, system on chip (SoC) devices have become increasingly popular in many applications, such as automotive, signal processing, portable electronic and communication products. In modern SoC design embedded memory dominates chip area and yield. Currently, embedded memory occupies over 60% of silicon area and therefore, embedded memory has become an important building block within a SoC device. As on-chip clock speeds continue to increase and SoC devices become heavily compact, limitations have been introduced in current automatic test equipment (ATE). In order to achieve high accuracy timing measurements, test circuitry is placed on-chip along side the device/module under test. This research focuses on on-chip low cost high resolution time measurement circuits for characterizing embedded memories that are capable of measuring a number of different types of time measurements, such as rise and fall times, pulse width and propagation delays.




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