The past decade has seen dramatic growth in the application of model checking techniques to the validation and verification of correctness properties of hardware, and more recently software systems. One of the methods is to model a hardware or software system as a finite, labelled transition system which is then exhaustively explored to decide whether a given temporal specification holds. Recently, there has been increasing interest in applying logic programming techniques to model checking in particular and verification in general. For example, table-based logic programming can be used as an efficient means of performing explicit model checking. Other research has successfully exploited set-based logic program analysis, constraint logic programming, and logic program transformation techniques.
The aim of this special issue is to attract high-quality research papers on the interplay between verification techniques (e.g., model checking, reduction, and abstraction) and logic programming techniques (e.g., constraints, abstract interpretation, program transformation).
Papers should be written in English, and formatted using the LaTeX style files developed by Cambridge University Press for TPLP. They can be downloaded from the directory: ftp://ftp.cup.cam.ac.uk/pub/texarchive/journals/latex/tlp-cls. The style files are tlp.bst and tlp.cls.
The extended submission deadline is 18 March 2002. Please either send six copies of your paper, or (preferably) email a PostScript or PDF file, to:
Michael Leuschel Dept. of Electronics & Computer Science University of Southampton Highfield, Southampton SO17 1BJ United Kingdom Email: firstname.lastname@example.orgAuthors are also requested to email a title and a four or five line abstract in plain text as early as possible to email@example.com to facilitate organization.