MS Thesis 

An Efficient Relaxation-based Test Width Compression Technique for Multiple Scan Chain Testing
Thesis Advisor Dr. Aiman H. El-Maleh      Committee Members: Dr. Sadiq M. Sait, Dr. Ahmad A. Al-Yamani
View Abstract    Preliminary Presentation   Defense Presentation      Thesis Text


Project Work

COE-561 Digital System Design and Synthesis
Term Report: Hardware/Software Partitioning and Scheduling Algorithms for Dynamically Reconfigurable Architectures
View Abstract       Report (.pdf 474KB)      Presentation (.ppt 242KB)

COE-572 Computer Aided Design of Digital Systems
Term Project: Parallelization of Simulated Evolution Metaheuristic for Multiobjective VLSI Standard Cell Placement on a Low-Cost Cluster
Presentation (.ppt 302KB). Also see published conference papers.

CSE-670 Design Issues of VLSI Programmable ASICs
Survey Report: A Survey of Logic Block Architectures for Digital Signal Processing Applications
View Abstract        Report (.pdf 575KB)       Presentation (.ppt 2928KB)

Term Project: Wormhole Run-Time Reconfiguration of FPGAs with Distributed Configuration Decompression
View Abstract        Report (.pdf 319KB)       Presentation (.ppt 280KB)

COE-586 Computer Arithmetic
Survey Report: A Comparative Study of Vector Dot Product Implementations on FPGA with Distributed Arithmetic and Residue Number System
View Abstract        Report (.pdf 305KB)       Presentation (.ppt 426KB)

Term Project: A Comparative Study of Different Multiply Accumulate Architecture Implementations on FPGA Using Distributed Arithmetic and Residue Arithmetic
View Abstract        Report (.pdf 113KB) & Appendix: Synthesis Results (.pdf 82KB)     Presentation (.ppt 207KB)    Xilinx Design Schematics (.zip 3.1MB)

CSE-551 Computer and Network Security
Term Project: Design Of a Reconfigurable Hardware for Efficient Implementation of Secret Key and Public Key Cryptography
View Abstract        Report (.pdf 420KB)       Presentations Part I (.ppt 1233KB) & II (.ppt 391KB)

COE-501 Computer Architecture
Term Project: A Configurable Simulator for Out Of Order Speculative Execution
Project Specification    Preliminary Presentation (.ppt 1186KB)  Final Presentation (.ppt 100KB)  Source Code (.zip 64KB)

CSE-661 Parallel and Vector Architectures
Term Project: Assessment of Parallelization Strategies of Metaheuristics for Linear Speed-up while Maintaining Quality
View Abstract        Report (.pdf 267KB)    Presentation (.ppt 414KB)

COE-540 Computer Networks
Term Project: Performance Evaluation of Gigabit Ethernet and Myrinet for System-Area-Networks
View Abstract        Report (.pdf 374KB)   Preliminary Presentation (.ppt 273KB)    Final Presentation (.ppt 143KB)