Corrections (1st edition)

There are two printings of the book to date. The second printing can be identified by a silver Companion Web Site logo on the front cover.

Where errors have been corrected in the 2nd printing, they are noted.


Page 22

Fig. 2.1 "XOB" should be "XOR". (Corrected in 2nd printing.)


Page 59

The alternative form suggested on the last line is wrong. This form would only work for a scalar range. So, if a had been declared as an integer, a range could have been used:

library ieee;
use ieee.std_logic_1164.all;
entity seven_seg is
  port (a : in integer range 0 to 15;
        z : out std_ulogic_vector(6 downto 0));
end entity seven_seg;

architecture with_select of seven_seg is
begin
  with a select
    z <= "1110111" when 0,
         "0010010" when 1,
         "1011101" when 2,
         "1011011" when 3,
         "0111010" when 4,
         "1101011" when 5,
         "1101111" when 6,
         "1010010" when 7,
         "1111111" when 8,
         "1111011" when 9,
         "1101101" when 10 to 15;
end architecture with_select;

The (incorrect) alternative has been deleted in the 2nd printing.


Page 95

The sensitivity list for the single process state machine example, at the bottom of the page is incorrect. Only clock should be in the sensitivity list, as the process should only change state or update outputs on a clock edge.


Page 121

The vector ranges for D and Q for the multiple bit shift register should be (n-1 downto 0), i.e.

library ieee;
use ieee.std_logic_1164.all;
entity reg is
  generic (n : natural := 4);
  port (D : in std_ulogic_vector(n-1 downto 0);
        Clock, Reset : in std_ulogic;
        Q : out std_ulogic_vector(n-1 downto 0));
end entity reg;

This has been corrected in the downloadable files.


Page 124

Fig. 6.10. The counter symbol should not have an inputs to the register stages.


Page 128

The self-correcting Johnson counter contains an error. The example in the text synthesizes with two different tools, but the line:

reg := (n-1 => '1', others => '0');

is not correct VHDL. At compile time, the value of n is not known. Therefore it is not considered to be locally static. Multiple choices within an aggregate are only permitted if all the choices are locally static. The following is also incorrect for the same reason:

reg := (reg'left => '1', others => '0');

The simplest solution is to replace this line with:

reg := (others => '0');

reg(n-1) := '1';

This error has been corrected in the 2nd printing and in the downloadable example files.


Page 133

Fourth line. The range 0 to 63 requires 6 bits, not 10 as suggested.


Page 134

The mode of RAS, CAS and WE is not shown in the example. In VHDL, the mode defaults to in.


Page 149

The last line of the 2nd paragraph refers to "the contents of MAR". This should read "the contents of MDR".


Page 190

The state coding is written incorrectly twice. The two lines should read:

attribute enum_encoding of state: type is "00 01 11 10";

and

enum_encoding : state = '00 01 11 10'


Page 208

Fourth line should read:

Fault F2 is a missing connection, causing R to grow from   to  .


Page 213

The PODEM example shows how to develop a test for H/1, not H/0 as stated. The example also refers to node D on lines 6 and 7. There is no node D, to avoid confusion with the D notation. The complete example should read:
 

We will use PODEM on the circuit of Figure 10.6 to develop a test for H/1. Initially, all nodes have an X value.

1. Set A=0. Fails – proposition 1 (H would be 1).
2. Set A=1. OK.
3. Set B=0. Fails – proposition 1.
4. Set B=1. OK. E=D, H=.
5. Set C=0. OK. F=0, I=.
6. Set E=0. Fails – proposition 2 (G=0, J=0, Z=0).
7. Set E=1. OK. G=1, J=1, Z=.

Therefore a test for H/1 is 1101/0


Page 219-20

The example of fault injection should include a component declaration for nand2 or the gates should be directly instantiated:

  g1 : entity work.nand2 port map (z, i0, i1, c0, c1, c2);
  g2 : entity work.nand2 port map (i0, y, i2, c3, c4, c5);
  g3 : entity work.nand2 port map (i1, x, i2, c6, c7, c8);
  g4 : entity work.nand2 port map (i2, x, y, c9, c10, c11);


Page 237

There is a reference to an exercise at the end of chapter 11 about designing an MISR. This exercise was accidentally omitted from the first printing.

Exercise 11.11

Modify the VHDL model of the LFSR from chapter 6 to implement an n-stage MISR. Hence, write a model of an n-bit BILBO register.
 
 

Answers to this exercise are included in the download example files for chapter 11.


Page 305

There is a missing semicolon in the answer to exercise 4.6:

n3 : nand2 port map (a(3), b(3), q);

This has been corrected in the 2nd printing and the download file.


Page 306-309

All 4 examples, 5.5, 5.8, 5.9 and 5.10 contain the same two errors:

There should be a begin between the signal declaration and the first process (seq).

The function rising_edge is not defined for type bit. Either replace the line with the rising_edge function with the line

elsif clock = '1' and clock'event then

or include a reference to the package with the rising edge function at the top of each example:

library ieee;
use ieee.numeric_bit.all;
 

Additionally, example 5.10 uses the label "seq" for the single process, but closes the process declaration with "end process com". Both names should be the same!

Moreover, in example 5.10, the assignments to the variable state are written as signal assignments. In all cases the assignments should read as, e.g.

state := S0;


Page 310

The piso example uses the srl operator on a std_ulogic_vector. srl is not defined for std_ulogic_vector, though it is defined for bit_vector. It is possible to overload the operator by writing your own "srl" function. It's easier to rewrite the line in the example:

reg := ('0' & reg(n-1 downto 1));


Page 311

The variable declaration for example 6.10 uses a constant n. n is not defined. For this example, use the declaration:

variable reg : std_ulogic_vector(2 downto 0);


Page 315

The sequence of TMS inputs in the answer to question 11.7 has an error. When in state Select-DR-Scan for the second time, TMS should be 0 to move to state Capture-DR:
 

State

TMS

TDI

Test-Logic-Reset

0

-

Run-Test/Idle

1

-

Select-DR-Scan

1

-

Select-IR-Scan

0

-

Capture-IR

0

-

Shift-IR

0

0

Shift-IR

1

1

Exit1-IR

1

-

Update-IR

1

-

Select-DR-Scan

0

-

Capture-DR

0

-

Shift-DR

0

0

Shift-DR

0

1

Shift-DR

0

0

Shift-DR

1

1

Exit1-DR

1

-

Update-DR

0

-

Run-Test/Idle

   

- means "don’t care". Change of state occurs on rising edge of TCK.


Thanks to Egbert Molenkamp, University of Twente, NL for several of these.

Thanks also to Marek Wegrzyn and his colleagues at University of Zielona Gora, Poland, who are translating the book into Polish and who spotted several errors.

And finally, the cover design that wasn't used! Put your sunglasses on before you click here!

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