The IEEE publishes all the VHDL standards. See http://standards.ieee.org.
See the comp.lang.vhdl FAQ for a full list. Many of the commercial tools listed below are available in a free, limited form for evaluation or student use. Alliance http://asim.lip6.fr/alliance/ has both a simulator and synthesis tool. The FreeHDL project http://www.freehdl.seul.org/ aims to develop a VHDL simulator for Linux. There is a VHDL mode for the Emacs editor, which includes templates for common constructs – http://www.emacs.org
This is not supposed to be an exhaustive list. Inclusion of a tool in this list does not imply endorsement of that tool. Omission of a tool does not imply any criticism of that tool.
Toolsets (Simulator + Synthesis)
Cadence – http://www.cadence.com
Synopsys – http://www.synopsys.com
Model Technology – http://www.model.com
Aldec – http://www.aldec.com
Dolphin – http://www.dolphin.fr
Several Verilog simulators are also available, e.g.
Simucad – http://www.silos.com
Synapticad – http://www.syncad.com
Synplicity – http://www.synplicity.com
Exemplar – http://www.exemplar.com
The final step in the design process is automatic place and route (APR) for an FPGA or ASIC. FPGA vendors generally supply their own APR tools. FPGA and CPLD vendors include:
Altera – http://www.altera.com
Xilinx – http://www.xilinx.com
Lattice – http://www.latticesemi.com
Actel – http://www.actel.com
Atmel – http://www.atmel.com
Cypress – http://www.cypress.com
Quicklogic – http://www.quicklogic.com