PLDs have an essentially AND/OR gating architecture. These days almost all have output macrocells to allow programming of features such as register latching of signals, tri-state enabling, register clock selection and feedback of various signals into the main AND/OR array. Complex PLDs (CPLDs) have sets of PLD-like architecture. PLD timing behaviour is essentially uniform and easily analysed, since propagation is through the standardised and regular AND/OR array and macrocells. PLDs tend to be used for "wide" processing applications such as address decoding and bus management. Most of the silicon is devoted to the arrays and parallel-form interconnect between large functional blocks. Each AND product term can have a potentially enormous number of inputs, while the OR gate will typically allow up to eight product terms to be combined. Some PLDs have systems for increasing this figure.
FPGAs have most of the silicon devoted to small-scale programmable blocks of logic functions - such as a five-input, three-output unit with two registers. Complex logic is produced by interconnecting this "fine grained" functionality. Most FPGA interconnect tends to be local (block to adjacent block), with a limited amount of global interconnect for signals such as clocks. This means that FPGA pin to pin timing depends critically on the "placement" of the blocks involved in a function, as well as the way the function is implemented in terms of the block facilities. FPGAs tend to be used for "serial" processing such as data encryption algorithms and sequence generation.
Virtually all my work on programmable logic has been with PLDs, particularly the 20 pin 18CV8 produced by ICT, and the 24 pin 22V10 produced by practically everybody (eg Lattice). I've also used various members of the PAL16 family, Xilinx 2000 and 4000 series, GAL16V8 and some of the Lattice isp1000 and isp2000 devices.
To turn a design specification into a file for programming an PLD, I have used PLPL for a decade. This freeware was produced by AMD long before they split off their programmable logic business as Vantis (now absorbed into Lattice), and has worked well for me - although I am very familiar with its limitations and features. You can download PLPL along with some documentation if you want to give it a try.
For ECS staff and students, PLPL - A PLD Designer's Guide with worked examples is on our Intranet, as is some other PLD documentation. Not available to outsiders for copyright reasons, sorry.
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Last updated 2000 July 14.
You can email me if you have any queries about PLDs - but I don't guarantee to know the answers.