Dr. Terrence Mak
Departmental web address:
Office address: Building 59/4219, Department of Electronics and Computer Science,
University of Southampton, SO17 1BJ, United Kingdom
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Invited Speakers 2016-2017
Dr Gianluca Tempesti, University of York, England
Title: Bio-inspired runtime adaptation in many-core systems
Imagine a many-core system with thousands or millions of processing
nodes that gets better and better with time at executing an application,
“gracefully” providing optimal power usage while maximizing performance
levels and tolerating component failures. Applications running on this
system would be able to autonomously adapt to the current status of the
hardware layer. In this context, two processes can be seen as crucial:
Graceful degradation implies that the system will be able to cope with
faults (permanent or temporary) or potentially damaging power
consumption peaks by lowering its performance.
Graceful amelioration implies that the system will constantly seek for
alternative implementations that represent an improvement from the
perspective of some user-defined parameter (e.g. execution speed, power
consumption). This kind of approaches bring electronics closer to the world of
biology, where organisms continuously adapt to the environment. It can
then become interesting to explore whether mechanisms inspired by the
operation of biological entities can be effectively exploited in the
world of electronics.
Dr. Gianluca Tempesti received a B.S.E. in electrical engineering from
Princeton University in 1991 and a M.S.E. in computer science and
engineering from the University of Michigan at Ann Arbor in 1993. In
1998 he received a Ph.D. from the Ecole Polytechnique Fédérale de
Lausanne (EPFL), Switzerland. In 2003 he was granted a young
professorship award from the Swiss National Science Foundation (FNS). In
2006 he joined the Department of Electronics at the University of York
as a Reader in Intelligent Systems. His research interests include
bio-inspired digital hardware and software, built-in self-test and
self-repair, programmable logic, and many-core systems, and he has
published over 80 articles in these areas. He is also CI in an EPSRC
Platform Grant and PI in an ongoing EPSRC grant ("Continuous on-line
adaptation in many-core systems: From graceful degradation to graceful
amelioration") that addresses self-optimization in many-core systems.
Dr Kenneth Tong, University College London, England
Title: Be Water My Friend
Abstract: Many people know the famous quote of Bruce Lee: “Empty your mind, be formless, like water”. Such concept has been proved very effective in Kung Fu, but can we apply such concept to our scientific research? In this talk, Dr Kenneth Tong, from UCL EEE, will share with you his experience in how water can replace its metallic counterpart and be used in wireless communications. How water’s formless feature can solve the problems in modern wireless communications. You may not see any board breaking demonstration, but hopefully it can inspire you to some new ground breaking ideas.
Bio: Dr Kin-Fai (Kenneth) Tong is a senior lecturer and member of the Sensors, Systems and Circuits Group at the Department of Electronic and Electrical Engineering (E&EE) in UCL. He has a strong track record in novel antenna design and microwave/millimetre-wave measurement in different applications such as radar, wireless communications, and medical related applications. During his PhD research, he has been credited to be one of the first who introduced the idea of embedding microstrip patch antennas into mobile phone handsets. His work in U-slot microstrip patch antennas has been cited more than 860 times to date. Before joining UCL, he was an Expert Researcher in the Photonic and Millimetre-wave Devices Group of the National Institute of Information and Communications Technology, Japan. He was awarded an Incentive Research Fund to work on the application of low-k materials to mm-wave antennas for efficient microwave and photonic monolithic integrations. He has co-authored three book chapters on planar antenna designs and over 130 journal and conference publications. Two of the papers Dr Tong co-authored have won the Duane F. Bruley Awards in 2012 and 2013 respectively. Dr Tong is a senior member of IEEE, Chartered Engineer of UK Engineering Council, Fellow of Electromagnetic Academy USA and Fellow of Higher Education Academy UK.
Prof. Leslie smith, Computing at Stirling University, Scotland
Title: Exploiting spike coding for sound analysis.
Sound can be coded in many ways, and we propose a biologically inspired
spike-based sound coding that maintains fine time structure and can code
over a wide dynamic range. We consider invertability of this coding, and
look at its use in finding onsets, segmenting sound, sound direction finding,
musical instrument recognition, and conclude with some current work on spike
based feature representation.
Bio: Leslie S. Smith: After graduating in Mathematics in 1973, went off to work
in the computing industry, but then returned to do a PhD in computing
at Glasgow, graduating in 1981. Initially he worked on parallel computing,
and taught at Glasgow, before arriving at Stirling University in 1984 and
becoming involved in neural networks and computational neuroscience.
On turning 40 he decided that he should also work on the auditory domain,
bringing together his interests in music and computation. He has also
worked on neuroinformatics, including helping create the CARMEN e-Science
portal, but currently he is most interested in biologically inspired early
auditory processing. He is Professor of Computing at Stirling University,
having stepped down three years ago from being Head of Department.
Vasilis F. Pavlidis, University of Manchester, United Kingdom
Title: Power Reduction Methods and Design Tools for 3-D ICs
Abstract: Energy-efficiency has become a predominant objective in the design of integrated circuits and systems.
Three-dimensional (3-D) integration supports enhanced power data and memory transfers due to the
proximity of the circuit components. However, the physical proximity offers limited power gains. In this
talk, I will demonstrate how voltage scaling – a standard low power method for integrated circuits – can
be applied in the context of multi-tier circuits demonstrating significant power savings without
compromising the system performance. An appropriate design flow to underpin the discussed approach
based mainly on commercial EDA tools is also discussed.
Power (and performance) also depends upon the developed temperatures within a circuit. In 3-D ICs,
higher temperatures are expected due to greater power densities. Accurately predicting the temperature
within a 3-D circuit is an important task. We have recently released an open-source thermal analysis tool
that can provide fast thermal map of 2-D or 3-D circuits at both the block and cell level including,
differently from other thermal tools, versatile system structures and the surroundings of the circuit. The
features of the tool and some related benchmarks will be presented in the second part of the talk.
Short-biography: Vasilis Pavlidis holds a BSc from Democritus University of Thrace, Xanthi, Greece and MSc and PhD
degrees from the University of Rochester, Rochester, NY, obtained in 2000, 2003, and 2008, respectively,
all in Electrical and Computer Engineering. From 2000 to 2002, he was with INTRACOM S.A., Athens,
Greece. In summer of 2007, he was with Synopsys Inc., Mountain View, CA. From 2008 to 2012, he was
a post-doc at the Integrated Systems Laboratory of EPFL, Switzerland. He is currently an Assistant
Professor at the Computer Science department of the University of Manchester within the Advanced
Processor Technologies group. His research interests are in the area of interconnect modeling and
analysis, 3-D integration, and other issues related to VLSI design. He is the leading author of the book
Three-Dimensional Integrated Circuit Design, (1st and 2nd Editions) and contributor to the Manchester
Peter Andres, University of Keele, United Kingdom
Title: Imaging and computational analysis and modelling of small biological neural system
The crustacean stomatogastric ganglion (STG) is a small, relatively autonomous nervous system containing two central pattern generator neural networks that control two sets of muscles in the gastric system of crabs and lobsters. This ganglion has 26 neurons in the brown crab and its anatomical connectivity, neurotransmitters and neuromodulators are well known. There are also detailed computational models of most neurons. The STG is a model neural system used for the studying of central pattern generators, neuromodulation and motor control. Voltage-sensitive dye neuroimaging allows the simultaneous recording of many (20+) neurons of the STG making possible the study of the system scale emergence of functionality from the behaviour of individual neurons.
This talk will review the voltage-sensitive dye imaging of the STG. I will discuss the measurement and assessment of the dopamine induced de-synchronisation of STG neurons. I will describe the analysis of the imaging data with the aim of reconstruction in fine detail of the simultaneous activity of multiple STG neurons. Finally, I will present results about the computational simulation of the functional variability of STG neurons.
Bio: Peter Andras is Professor of Computer Science and Informatics and Head of Computing in the School of Computing and Mathematics at Keele University. Previously he worked in the School of Computing Science of Newcastle University. He got his degrees from the Babes-Bolyai University, Cluj, Romania. His research is about the role of information processing in complex systems. This includes analysis of complex networks, agent-based modelling of social systems, analysis and modelling of neural systems and the development and application of computational intelligence methods. He is Senior Member of the IEEE and Fellow of the Royal Society of Biology.
Dr Dinesh Pamunuwa, Bristol University, United Kingdom
Title: Nanoelectromechanical (NEM) relay-based circuits for high-temperature and radiation-hard electronics
Digital circuits based on nanoelectromechanical (NEM) relays hold out the potential of providing an energy efficiency unachievable by conventional CMOS technology. Further, they can withstand much higher temperatures and absorbed radiation doses, offering ground‐breaking improvements for harsh‐environment operation. The main challenges are in achieving reliability over a sufficient number of hot switching cycles, miniaturisation and integration. These challenges are being addressed through innovations at the material, device architecture and circuit levels by different groups around the world. This talk will give an overview of the challenges and opportunities in NEM relay‐based computing, drawing on experiences drawn from three multi‐partner projects involving the University of Bristol, NEMIAC (EU grant 288670), NEMRAD (UK DSTL grant CDE38104) and NEMICA (UK Innovate grant 61931‐453231).
Dinesh Pamunuwa (M’04─SM’09) received the B.Sc. degree (with honours) in Electrical and Electronic Engineering from the University of Peradeniya, Peradeniya, Sri Lanka in 1997, and the Ph.D. degree in Electronic System Design from the Royal Institute of Technology (KTH), Stockholm, Sweden, in 2003. He interned at the Berkeley Research Labs of Cadence Design Systems in Berkeley, CA during his PhD, working on timing and signal integrity analysis in integrated circuits. During this period, he cofounded an electronics and software consultancy company based in Sweden and Sri Lanka. He was appointed to a Lectureship at Lancaster University in May 2004 and made a Senior Lecturer in 2010. He joined the Electrical and Electronic Engineering Department of the Merchant Venturers School of Engineering, University of Bristol as a Reader in Microelectronics on 1 Dec, 2011.
Dinesh has carried out research in the field of VLSI since 1999, focusing on the realisation of the next generation computing platforms for ultra‐high performance and energy efficiency. The areas he has worked on include interconnect design and signal integrity issues, methodologies and architectures for electronic system design and networks‐on‐chip, architectures for nanoelectronics and nano‐electro‐mechanical (NEM) relay based circuit design.
Mbou Eyole, ARM Ltd, United Kingdom
Title: The Next-Generation Vector Architecture for HPC
ARM’s next-generation vector architecture known as the Scalable Vector Extension (SVE) has been created primarily for energy-efficient high-performance computing (HPC) designs.
SVE has emerged as a key ingredient in the race towards Exascale computing and has features aimed at meeting the ever-increasing computing demands of scientific research in domains such as meteorology, astronomy, quantum physics, and fluid dynamics.
In this presentation, I will go through the design of the SVE architecture, from the set of design requirements and constraints to various instruction set components. I will explain why a Vector-Length-Agnostic approach was adopted in the design of the architecture and how it works in practice. I will also explain results obtained from measuring the performance of critical kernels taken from standard HPC benchmark suites, and highlight any scalability issues that were encountered.
Bio: Mbou Eyole is a processor research engineer at ARM. He is responsible for creating next-generation architectures and has been a key contributor to ARM’s new vector architecture called the Scalable Vector Extension. He is a Chartered Engineer and has filed over 14 patents on CPU architectures, instruction set extensions, and microarchitectures. His research focuses on improving the applicability of SIMD architectures to a broader range of workloads which have high computational demands. In particular, he wrestles with the problem of irregular computation pathways and non-affine memory accesses in parallel workloads. He also has significant experience in sensor network design and in his PhD (University of Cambridge, 2008) he proposed a multi-layered decentralised model of distributed computation with energy-efficient multicore nodes managing sub-clusters of sensor nodes. Before joining ARM, he was a Research Fellow at Trinity College, Cambridge, where he investigated scheduling in massively parallel architectures.
Dr Piotr Dziurzanski, Staffordshire University, United Kingdom
Title: Resource allocation in multi-modal real-time applications
This talk considers an energy-aware resource allocation approach dedicated to hard-real-time systems with distinctive operation modes. The current mode of a system under consideration can be detected during run-time. In the presented approach, a Naive Bayes classifier observes the latest execution times of processes. When a mode change is detected, the processes migration is performed to decrease the number of active cores leading to considerable energy savings while still not violating any of the timing constraints. The proposed approach consists of both off-line and on-line steps, whereas more computational intensive steps are performed off-line.
During the talk, an automotive use case, a simple engine control unit, is used to illustrate the issues, but the technique is applicable to assorted application domains.
Bio: Piotr Dziurzanski received the MSc and PhD degrees in computer science from West Pomeranian University of Technology (Poland) in 2000 and 2003, respectively. From 2003 to 2012 he worked as an assistant professor at the same university. In 2013 and 2014 he joined the DreamCloud project as a research associate at the University of York. He currently works as a lecturer at the Staffordshire University (UK) in the Faculty of Computing, Engineering and Sciences. His scientific interests include embedded systems, hardware-software co-design, on-chip multiprocessor systems and distributed computing.
Prof Maurizio Palesi, University of Catania, Italy
Title: On-Chip Approximate Communication for Energy Efficiency
On-chip communication in Network-on-Chip (NoC) based manycore architectures accounts for a significant fraction of the overall energy budget. In fact, as the number of cores increases, the average communication hop count increases as well, with a consequent impact on the average energy per transmitted bit. Several techniqes have been proposed in literature for improving the energy efficiency of NoC based architectures, including, optimized network topologies, low-power router architectures, application-specific routing algorithms, mapping techniques, etc. All of them assume an underlying reliable communication fabric which exposes an almost insignificant low bit error rate (BER). In this seminar we discuss the possibility of relaxing the reliability assumption of the communication system with the consequent increase of the BER for specific communication flows. The rationale behind such proposal is that not all the communications have the same reliability requirements. For instance, consider a multimedia application in which a flow of pixels is transmitted to a specialized core for some kind of manipulation. If some of the pixels have been affected by errors during their transmission, it might not represent a disruptive event, if not just a degradation of the quality of the final image that is some cases can be fully tolerated. Of course the admittance of such detrimental events must be counterbalanced by the improvement of other design objectives, for instance, power saving, performance improvement, etc. In fact, there is an emerging class of applications, namely, recognition, mining and synthesis (RMS) which show a "forgiving" nature towards computational errors which is exploited by what it is known as approximate computing. This seminar aims at motivating the opportunity of extending such concept to communication by defining a set of approximate communication techniques aimed at improving the energy efficiency of the NoC.
Bio: Maurizio Palesi is an Associate Professor in Information Processing Systems at University of Catania, Italy. Dr. Palesi is an Associate Editor of STM Journal Engineering Science Letters, Recent Trends in Parallel Computing, Hindawi Advances in Electrical Engineering, Elsevier Computers and Electrical Engineering Journal, Conference Papers in Engineering, Computer Engineering section, Hindawi VLSI Design Journal, and Computer Science Journals. He has served as Guest Editor for Elsevier Microprocessors and Microsystems: Embedded Hardware Design, IET Computers & Digital Techniques, ACM Transactions on Embedded Computing Systems, Journal of Parallel Computing, International Journal of High Performance Systems Architecture. He also co-organizes several special sessions and workshops including IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), ACM International Workshop on Network on Chip Architectures (NoCArc) in conjunction with the Annual IEEE/ACM Int. Symposium on Microarchitecture (MICRO), Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools and Applications in Design and Test Conference in Europe (DATE), ACM International workshop on Many-core Embedded Systems (MES) in conjunction with ISCA. He is in the Technical Program Committee of several IEEE/ACM International Conferences including DATE, RTAS, CODES+ISSS, ESTIMedia, NOCS, SOCC, VLSI, ISC, and SITIS. He is a member of IEEE and has published 1 book, 6 book chapters, and over 110 refereed international journals and conference papers and was awarded the Best Paper Award at DATE 2011. Dr. Palesi is member of the European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC). His general research area is embedded systems design. His research activity is mostly related on single-chip implementations of complete embedded systems, known as Systems-on-Chip. Specifically, his main research contributions are in the area of multi-objective optimization, methodologies for design space exploration, low-power design, and Network-on-Chip architectures.
Prof Leandro Soares Indrusiak, University of York, England
Title: Network-on-Chip Platforms for Real-Time Mixed-Criticality Applications
Abstract: Network-on-Chip (NoC) is a widely used on-chip interconnect architecture for large multi and many-core processors. NoCs provide packet-switching infrastructure for multiple types of system-wide communications, such as message passing between tasks running on different cores, data transfers between external memories and local scratchpads, or paging and coherency mechanisms for multi-level caches. In all cases, the performance of the NoC affects system timeliness and thus must be taken into account when analysing application-level real-time guarantees. This is specially true when application tasks and communication packets of different levels of criticality share the NoC infrastructure. This talk will introduce and motivate a communication-centric design approach to multi and manycore systems, with special emphasis to the use of priority-preemptive virtual channels. Then, it will review the state-of-the-art in schedulability analysis for those NoC architectures, enabling safe upper bounds to end-to-end latencies (i.e. tasks and respective communication packets). Finally, it gives an insight on how schedulability analysis can be used as a fitness function in a search-based optimisation process, aiming to find NoC configurations that meet performance guarantees and optimise energy dissipation.
Bio: Leandro Soares Indrusiak is a faculty member in the Department of Computer Science at the University of York. He is part of the Real-Time Systems group, with technical contributions in the areas of systems and networks with timing and energy constraints. He has more than 100 peer-reviewed publications in the top conferences and journals in real-time and embedded systems, design automation and high-performance computing. Over the past decade, he has supervised and graduated seven doctoral students, has held visiting faculty positions in five different countries, and has led projects funded by the European Union, research councils of the UK, Germany and Brazil, as well as several companies. Dr Indrusiak holds a bi-national doctoral degree jointly issued by UFRGS (Brazil) and TU Darmstadt (Germany) in 2003, is a member of the European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), and a senior member of the IEEE.
Dr Tobias Becker, Maxeler Technologies, UK
Title: Dataflow Computing: Enabling Exascale and Cloud HPC
Abstract: The computing industry is facing unique challenges as the salient demand for computational performance combined with energy efficiency continues to grow while at the same time performance and efficiency gains from conventional CPU technology continues to stagnate. Maxeler Multiscale Dataflow Computing is a new paradigm that addresses these
challenges through an new model of computation that splits
conventional programs into a controlflow part and a dataflow part,
while making the data plane fully programmable. The benefits of this
approach have already been realised across a range of application
domains, typically delivering one to two orders of magnitude
improvements in terms of performance and energy efficiency compared to
conventional servers. In this talk we focus on the next steps for
dataflow computing, making its way towards exascale and public cloud
Bio: Tobias Becker is the Head of MaxAcademy at Maxeler Technologies where
he coordinates Maxeler’s research activities and university relations.
Before joining Maxeler he been a research associate in the Department
of Computing at Imperial College London. He received a Ph.D. degree in
Computing from Imperial College London and a Dipl. Ing. degree in
Electrical Engineering from the Technical University of Karlsruhe (now
KIT). His research interests include reconfigurable computing, custom
accelerators, adaptive computing, low-power optimisations, and